Package-on-package (PoP) is becoming an increasingly popular integrated circuit packaging technique because PoP allows for higher density electronics.
In a conventional package-on-package process, a first package component such as an interposer is mounted onto a second package component such as a package substrate. A semiconductor chip may be mounted on the interposer using flip-chip bonding. An underfill may be dispensed into the gap between the semiconductor chip and the interposer to prevent cracks from being formed in solder bumps or solder balls. Cracks are typically caused by thermal stress and warpage. The thermal stress and warpage are caused by thermal expansion mismatch between the components of a package-on-package structure. Even with the use of underfills and interposers, the problem of warpage still cannot be entirely eliminated.